1.

This board is based on the standard 6U VPX architecture and is a general-purpose high-performance signal processing platform. It is independently developed by our company. The board uses a TI DSP TMS320C6678 and a Xilinx Virtex 7 series FPGA XC7V690T-2FFG1761I as the main processor, and Xilinx's Aritex XC7A200T as the auxiliary processor. The XC7A200T is responsible for managing the power-on timing, clock configuration, system and module reset, program reconfiguration, etc.

2. Design Reference Standard

• VITA46.0 VPX Base Standard
• VITA46.3 Serial RapidIO on VPX Fabric Connector
• VITA46.4 PCI Express on VPX Fabric Connector
• VITA46.7 Ethernet on VPX Fabric Connector

3. technical index

• The data rate is 1333MHz;
• DSP plug-in NorFlash capacity 32MB;
• DSP adopts EMIF16-NorFlash loading mode;
• DSP connects one 1000BASE-T Gigabit Ethernet to the front panel;
• DSP connects one line 1000BASE-T Gigabit Ethernet to VPX P4;
• Connect PCIe x2 to VPX P2;
• Two clusters of DDR3 are attached to the FPGA. Each cluster has a capacity of 4GB, a bit width of 64 bits, and a total capacity of 8GB. The data rate is 1600MHz;
• FPGA plug-in NorFlash capacity 128MB;
• The loading mode of the FPGA is BPI mode;
• FPGA external 2-way FMC-HPC;
• Connect GTH x8 to VPX P1;
• Connect GTH x4 to VPX P2;
• FPGA connects one QSFP plus to the front panel; the optical port rate is 40Gbps;
• DSP and FPGA are interconnected through SRIO x4 @ 5.0Gbps /per Lnae;
• DSP and FPGA to implement GPIO and SPI interconnection;
• DSP and CFPGA to connect GPIO,SPI, and EMIF;
• FPGA and CFPGA to realize GPIO interconnection;
• CFPGA connects 1000BASE-T Gigabit Ethernet to VPX P4.
• boards require industrial chips. The structure meets the seismic requirements.

4. physics

working temperature: commercial grade 0 ℃ ~ +55 ℃, industrial grade -40 ℃ ~ +85 ℃
working humidity: 10% ~ 80%

5. power supply requirements

single power supply, power consumption of the whole board: 40W

voltage: DC +12V,5A

ripple: ≤ 10%

6. application field

signal processing, radio communication field.

Integrated Application of 7. Acquisition, Storage and Computing

In this application mode, VPX is used to expand the backboard and access four M.2 SSDs.

PCIE3.0 x4 interface is used between each storage disk and FPGA, which can give full play to the performance of a single storage disk. For example, if the continuous read-write bandwidth of a single disk is ≥ 2GB/s, the continuous read-write bandwidth of the storage array of a single disk is ≥ 2GB/s; When multiple disks work in parallel, the read-write bandwidth of the storage array increases exponentially, 2 disks are ≥ 4GB/s,4 disks are ≥ 8GB/s, and so on.

The storage capacity of the storage array is determined by the single disk configuration. Currently, the storage capacity of a single NVME storage disk can be 512GB, 1TB, 2TB, 4TB, 8TB, and 16TB. For example, if you configure 4 storage disks, the storage array capacity can reach up to 64TB.

hard disk management is through the file system, the PCIeX4 of FPGA is interconnected with the 6U VPX motherboard, and the operating system directly maps and manages the hard disk. It can also be exported to other server devices through the front panel QSFP + optical fiber.

FMC sub-card can expand high-speed AD,DA, 8-channel optical fiber, image sub-card, etc.

The advantage of this solution is to integrate collection, storage, and computing, reduce hardware costs and power consumption, and reduce equipment volume and weight. The problem is that FPGA programs are highly integrated and difficult to develop.